The invention relates to the field of receivers, and in particular to receivers having timing recovery subsystems.
Enabling a synchronous transmission between a transmitter and a receiver typically requires a transmitter and receiver to be in phase and frequency lock with respect to a reference clock signal. One such system in which phase and frequency lock is needed for synchronous transmission is an Asymmetrical Digital Subscriber Line (ADSL) system.
ADSL systems are one of a family of related standards and technologies providing for so-called broadband data communications to subscribers over the existing twisted-pair copper wires used in the telephone network's local loops. ADSL systems take advantage of the fact that the twisted-pair wires can transmit data at frequencies higher than the 4 Khz imposed on the voice channel by the telephone network's voice digitizing equipment. Generally, data is transmitted downstream (i.e. towards the subscriber) using a larger portion of the high frequency band than data transmitted upstream.
One type of ADSL implementation uses a transmission scheme known as discrete multitone (DMT), conceptually illustrated in FIG. 1a. Rather than using a single channel for upstream and downstream transmissions, DMT divides the frequency spectrum above the voice band 100 into a number of 4.3125 kHz wide channels 102. Channels 102 are also known as bins. In a typical ADSL system, each bin corresponds to a carrier signal whose frequency is a multiple of 4.3125 kHz and there are approximately 256 bins.
The data to be transmitted in each channel is encoded using IFFT/FFT techniques and is equivalent to quadrature amplitude modulation techniques as conceptually illustrated in FIG. 1b. Refer to ADSL standard. Generally, a DMT symbol is transmitted during consecutive periods of time T. The DMT symbol is the sum of carrier signals in all bins whose phases and amplitudes are derived from the data being modulated in each bin. Thus, the amplitude and relative phase shift combination in each period is representative of the bits to be transmitted during that period. While amplitude modulation has not been illustrated for clarity of the phase shift illustration, FIG. 1b shows the phase of a carrier signal being changed in relation to the modulating data. For instance, a data symbol modifies the phase of a carrier signal during period 112 from the previous signaling interval by one-half the wave period 110. Similarly, the phase of the carrier signal during period 114 is shifted by one-quarter the wave period with respect to the carrier signal during period 112.
To recover the encoded data, the received signal must be sampled over the transmission period T and the phase shift and amplitude of the carrier signals have to be accurately determined for each period. A typical ADSL receiver for recovery of the encoded data is illustrated in FIG. 2a. A received signal r(t) is first pre-filtered using a pre-filter 202. Pre-filter 202 corresponds, for example, to a 4th order butter-worth filter with a 2.5 MHz cutoff frequency. After being filtered, the signal is sampled using an analog-to-digital converter (“A/D”) 204. A/D 204 operates at a sampling rate of, for example, 8.832 MHz. A post filter 206 then processes the digitized signal. As shown in FIG. 2b, post filter 206, during the timing recovery phase of the system operation, includes a decimator 208, a data buffer 210 and a Fast Fourier Transform (FFT) signal processor 211. Decimator 208 filters and decimates the digitized signal. The outputs of decimator 208 are then buffered in buffer 210 to create a data frame whose duration is equal to the symbol period T. For example, when the symbol rate is 4.3125×103 symbols per second, the buffered data frame's duration is 1/4.3125×103 seconds. For the examples given, a decimation factor of four provides enough samples to satisfy the Nyquist criterion for the frequency of the highest carrier, and results in 512 samples in a buffered data frame.
FFT processor 212 takes the FFT of the data frame and enables recovery of the transmitted data. The FFT of the buffered data per bin corresponds to a constellation point with amplitude A and phase φ. Detector 214 detects this constellation point, determines the data associated with the constellation point and outputs this data as ad.
Since the transmitted data is encoded in the amplitude and phase of the received signal, it is important that the normalized sampled phase, φ, closely approach the transmitted phase of the signal Φ in order for the detector to function properly. To achieve this, the receiver and transmitter need to be in phase and frequency lock with respect to a reference clock signal. In the transmitter, the reference clock signal is used to generate the signals transmitted to the receiver, while the reference clock is used in the receiver to drive the A/D clocking signal. In an ADSL system, the reference clock signal is generated at the Central Office site. The receiver clock is synchronized in phase and frequency to the clock at the Central Office by performing timing recovery on the received signal. Therefore, the receiver must recover timing information from the received signal at appropriate sampling instances tk Generation of the pilot tone derived from the reference clock at the at the Central Office, and transmission of the pilot tone to the receiver, enables the receiver to achieve phase lock with the transmitted pilot, and to lock the oscillating frequency of its local oscillator to that of the transmitter.
For an ADSL receiver, this timing recovery has generally been performed via a conventional Digital Phase Lock Loop (DPLL) timing recovery subsystem. Timing recovery subsystem comprises a timing-error detector (“TED”) 216 followed by a loop filter 218, an oscillator whose frequency is proportional to its input control voltage, i.e. a variable controlled oscillator (VCO) 220, and a zero crossing detector 222.
The pilot tone is transmitted with a given amplitude A, a given phase Φp and with a frequency of n*4.3125×103, where n represents the bin number allocated to the pilot tone. The transmitted phase corresponds to a known phase (e.g., for ADSL it is 45°), which is used by TED 216. Receiver 200 operates as described above to produce an FFT of a received DMT symbol of duration T. The output of the FFT for the pilot signal for each symbol period corresponds to an amplitude A, and phase, φp. A constant value of φp over multiple DMT symbol time periods, and a value of φp equaling Φp occurs when the clock to generate the pilot tone at the transmitter and the clock for the receiver A/D are in phase and frequency lock.
The phase, φp is also input to TED 216, while TED 216 knows Φp a priori. For initial timing recovery, TED 216 then produces an indication xk of the sampling phase error Δ=φp−Φp. That is, TED outputs an error signal proportional to the difference between φp and Φp:xk=kd(φp−Φp)where kd represents the timing error detector gain. This output, upon being filtered by loop filter 218, is used as the input to VCO 220 to control the VCO's frequency output. The output signal of VCO 220 is then applied to zero crossing detector 222 to generate pulses, which are used to generate a clock for A/D 204.
A digital proportional-plus-integral loop filter 300, as shown in FIG. 3, with weighting factors Kp and Kf, is normally used in conventional DPLL timing recovery subsystems. This architecture simultaneously corrects initial frequency and phase offsets present between a received and a locally generated signal. Initial frequency and phase offsets are simultaneously corrected by the output of the loop filter adjusting the VCO frequency in small increments until the receiver and transmitter are in phase and frequency lock.
During initial timing acquisition, the loop filter's bandwidth is increased in order to accelerate signal acquisition, at a cost of allowing a decrease in the signal-to-noise ratio. Upon acquisition, the values of Kf and Kp are decreased to decrease the loop bandwidth, thus reducing the noise-based perturbations.
While the loop bandwidth is varied in a typical ADSL to increase the acquisition time, the loop bandwidth is still generally kept small to combat noise. This results in a long overall response time for the initial locking of phase and frequency, while shorter response times are generally desirable.